Mentor Graphics Corp., the high-performance system verification solutions, announced the third generation of TestBench Xpress, the industry’s only commercially proven RTL-accurate virtual emulation capability that eliminates the traditional barriers of adopting hardware in-circuit emulation for system-level integration. When used in conjunction with Mentor’s Veloce family of hardware assisted verification products, TBX provides a software-based, cost-effective and efficient way to perform hardware-software co-verification for embedded systems.

The third generation of TBX version delivers megahertz-class acceleration compliant with IEEE’s Standard Co-Emulation Modeling Interface. It is architected based upon SystemVerilog Direct Programming Interface to deliver up to 10,000X performance improvement over the fastest software simulator without compromising interoperability and debug visibility. It also provides backward compatibility with the previous generation standard SCE-MI 1.1. The new transaction compiler de-couples the software simulator from the high-performance Veloce family to accomplish an optimal mix of bandwidth and communication latency.

Productivity-enhancing Features

The new TBX comes with a series of productivity enhancement features to allow integration with existing functional models as well as high-level architectural models coded in C/C++, SystemVerilog or SystemC.

Optimal performance due to ability to perform streaming transactions to and from SystemVerilog based implementation using Transaction Pipes as mandated by the SCE-MI 2.0 standard. TBX completely supports both SCE-MI 1.1 and SCE-MI 2.0 standards. Various clock optimizations in TBX allow ICE-like performance and throughput in transaction based target-less applications.

Broad language support, allowing users to develop their test environment and complex SoCs with newly added HDL and SystemVerilog language constructs that extends the support over and above synthesizable subset of SystemVerilog for higher efficiency and productivity.

Efficient and standards compliant modeling for transaction based verification with un-timed test environment modeled in C/C++/SystemC and timed transactors and complex SOC DUT modeled in SystemVerilog provides for increased productivity while maintaining MHz class performance.

Language compliance with the SCE-MI standard, via a transactor linting mechanism that automatically checks the language compliance with the SCE-MI standard and generates detailed reports to facilitate development of performance optimal transactors.

Debug productivity in conjunction with the built-in debug infrastructure of Veloce hardware-assisted engine, providing simulation-like debug environment with full visibility over all design signals and module-level control of system tasks.

Efficient database management enabling simultaneous usage of a design database by several users without consuming additional disk space. This facilitates optimal usage of the disk space as users deploy multi-million gate chips through transaction driven verification.

- Cost-effective scalability. Soft models built for TBX provide unsurpassed flexibility and avoid additional board and hardware development, which are typical during traditional emulation projects. Eliminating the need to develop and maintain target systems for each project minimizes direct costs and saves engineering resources for debugging platforms under development.